IC Diagnosis: Industry Issues

Forensic microelectronics space age silicon science or barbarian bloodletting? Corporate lifesaving laser surgery or clumsy caveman carving to a slow death? Is our ability to diagnose a failing IC still in the stone age? At times it seems so, particularly when the production test data provides no more insight than a cryptic “FAIL” flag and the design provides no testability avenues. Despite recent innovative techniques, the analysis journey may follow a crude path, fraught with pitfalls, dead ends, and chances to destroy all evidence of the root cause of failure. Is there hope that this situation will improve? Yes, since we already have a variety of methods to take us from brute force into automation. Automated diagnosis is still in its infancy and is therefore highly dynamic, with no clear direction at present but many opportunities. Members of the SEMATECH Product Analysis Forum are working valiantly to bring visibility and focus to the joint development of solutions, including software-based diagnosis tools. Driving this need is the continued increase in IC complexity. The IC quality and reliability issues of cost, schedule, and performance are mirrored in the critical diagnosis aspects of cost effectiveness, turn-around time, and accuracy of analysis. The value of in-process wafers and packaged ICs represent a major economic risk for a company. If a problem is not detected and resolved promptly, the companies’ survival can literally hang in the balance. The cost of a yield crash, missed market target, performance problem, or reliability issue can easily drain the financial resources of any company. The trend is ever-faster IC technology advancement, with increasing risk due to the inherent difficulty in diagnosing problems rapidly on complex circuitry. The industry has worked through tough problems in the past, but we need better strategies for thriving in these changing times. Proactive and cooperative efforts are required to accomplish this in the face of corporate cost reduction and workforce downsizing that have directly impacted the development of new diagnosis capabilities. It is, in no small way, a result of reduced budgets and human resources that more automated diagnosis tools must be created. Many analysis laboratories simply do not have the time or resources to do more than struggle to keep up with the high priority problems of the day, let alone spend time developing and implementing alternatives to traditional, brute force analytical methods. Without modern tools and techniques to make their work satisfying and successful, analysts will simply change to other jobs with more rewards, including higher pay. The challenges of diagnosis coexist with those of testing, both of which are inherently intertwined with and dependent upon the IC design. As with the difficulties of achieving high test coverage, reaching high diagnosability requires design support. Without it, the task parallels that of trying to test all logic state space of any modern IC it simply can’t be done. We design ICs with logic complexity well beyond our ability to test and diagnose completely. The industry is struggling to maintain adequate test capabilities, particularly for state-of-the-art microprocessors and DSPs. However, diagnosis has yet to approach, at least from an industry-wide methodology, even this level of investment. A new failure analysis paradigm is necessary a shift from hardware-based techniques to software-based methods. The transition is a daunting task because of its complexity. We understand the ideal end state a suite of software tools that determine the root cause of failure using electrical testing data and design/technology information. As with other successful practices in microelectronics, including design and testing, it is expected that a suite of software applications will be necessary to thoroughly diagnose complex ICs. These tools should be able to run concurrent with or independent of production testing. When running concurrent with testing, they should be able to provide at least a pareto distribution of the dominant failure modes & mechanisms. Approaches include electrical behavior description using defect classes and high level heuristics compatible with VHDL design tools. It is critical that those working in IC design and test understand the rapidly increasing need for software diagnosis tools and support their development for the semiconductor industry.